The advanced fabrication techniques are driving the electronic products to an ever smaller scale, making them more compact and complex. On the other hand, as the integrated circuit (IC) technology advances, the requirement on transmission speed between circuit components increases tremendously. Optoelectronic interconnects are an attractive solution to the bandwidth limitation of data transmissions for board level interconnections. A typical integrated optical-electrical circuit includes a laser source in the transmitter, a photo detector in the receiver, and an optical waveguide connecting the transmitter and receiver. The optical waveguide is a physical structure including transmission medium, such as optical fibers, that transmits and guides light signals from the transmitter to the receiver.
The speed, date rate, power, and size of optoelectronic devices generally scale with the wavelength of the light signals. Nowadays, the complexity of two-dimensional (2D) photonic modules is limited by their substrate sizes and the difficulty in connecting large numbers of electrical connections. Also, the high-profile of these packages prevents them from usage in many applications, e.g., portable electronics products. The 2D system on chip (SoC) technique can reduce the size and increase the performance, but limits the flexibility and posts challenges on fabrication process. For example, during the fabrication process, different materials, e.g., Si and GaAs, must be combined on the same chip.
On the other hand, three-dimensional (3D) IC techniques allow a better integration of devices with different materials and achieves a dramatic cost and labor reduction. A 3D integrated circuit includes two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. Novel combinations of materials/geometries allow for devices far superior than their 2D in-plane counterparts. Additional flexibility can be achieved in package design, interconnect routing, and package placement through 3D bare-chip integrations.
In “SMT-compatible large-tolerance ‘OptoBump’ interface for interchip optical interconnections,” IEEE Transactions on Advanced Packaging, Vol. 26, No. 2, May, 2003, Ishii et al. lay open an “OptoBump” interface for inter-chip optical interconnections having an embedded optical polymer waveguide. However, the optical chips are packaged in a 2D thick module, and thus large holes on the PCB are required. Because the optical and electrical ICs are packaged in a module at a large distance from the waveguide, the system requires collimating or focusing lenses on the electrical modules and on the PCB, resulting in poor electrical and optical performance and higher costs. In addition, the high-profile design restricts its implementation in many portable products.
In U.S. Patent Application Publication No. 2005/0089264, Johnson et al. lay open an optoelectronic card and PCB including a passive alignment between the Vertical Cavity Surface Emitting Laser (VCSEL) devices and waveguides. In there, a self-alignment characteristic or flip chip is utilized during the solder reflow to assemble the VCSELs to the waveguide on the surface of a PCB. In Johnson's system, both the VCSEL and optical waveguide are sitting on top of the PCB, and thus the integration is poor.
In “Terabus: tebrabit/second-class card-level optical interconnect technologies,” IEEE Journal of Selected Topic in Quantum Electronics, Vol. 12, No. 5, September/October 2006, Schares et al. lay open an optoelectronic device having a VCSEL and its driver chip (or a photo diode and its receiver chip) supported by a silicon carrier. In there, the optical polymer waveguide and all the circuit components are not embedded, and thus the package is too thick to be useful for most portable products. In addition, because silicon carriers with holes are used to support the chips and optical lenses are required, the material and production costs are inevitably high.
In “300-Gb/s 24-channel bidirectional Si carrier transceiver optochip for board-level interconnects,” Proceedings of 58th ECTC, Electronic Components and Technology Conference 2008, pp. 238-243, May, 2008, Doany et al. lay open a bidirectional transceiver optochip supported by a silicon carrier, which is attached on a standard plastic ball grid array package. However, in Doany's system, the polymer optical waveguide is not embedded, but on top of the PCB. The optical and electrical ICs are packaged in a carrier with a very long distance to the optical polymer waveguide, thereby requiring collimating or focusing lenses in the package and on the PCB. In addition, the IC components are not integrated in a 3D stack structure, thereby occupying large footprint and rendering the device unsuitable for portable products.
U.S. Pat. No. 7,373,033 to Lu et al. describes a chip-to-chip optical interconnect including a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via. In there, not all of the electrical and optical chips are embedded and a carrier is used to support the chip, thereby rendering the package too thick to be useful for most portable products. In addition, the electrical and optical chips are not stacked in a 3D IC structure, causing the package to occupy a large footprint as well as compromising the performance.
U.S. Pat. No. 6,243,509 to Chen describes a board level optoelectronic interconnects having an embedded optical polymer waveguide and the optical chips. However, the semiconductor devices in the system are not embedded. The electrical and optical chips are not integrated in a 3D stack structure, thereby causing the package too large to be applied to most portable products and comprising the performance of the device.
As discussed above, in existing 3D optoelectronic devices, the electrical and optical chips are not integrated in the 3D circuit structure, which can be embedded with the optical waveguide. As a result, the footprints of the circuit components are not optimized and the systems do not achieve the optimal performance. As the trend towards miniature and faster electronic products continues, innovative structures and fabrication process for improving optoelectronic circuit package and lowering material and fabrication costs are highly desired.